(*==========================================================================*)
(*====================== ASYNCRONOUS TRANSMITTER ===========================*)
(*==========================================================================*)
(****************************************************************************)
(*                                                                          *)
(* PRIMITIVE : ASYN__TXD                                                     *)
(* Written by: Ewald Liess, Motorola Munich (0049) 89/92103-574             *)
(* Date      : 25/08/90                                                     *)
(*                                                                          *)
(* Valid State Entry Conditions:                                            *)
(*  State HSR0  HSR1  M/TSR  LSR  Pin  Flag0          ACTION                *)
(*    1     1     1     x     x    x     x     Initialise Pin State         *)
(*    2     0     0     1     x    x     0     Test the TDRE-Bit            *)
(*    3     0     0     1     x    x     1     Setup next Bit-transmission  *)
(*                                                                          *)
(*  flag0: Transmitter active (Polling TDRE-Bit)                            *)
(*  flag1: Transmission running (START-Bit is transmitted                   *)
(****************************************************************************)

(* %org 0. *)
(* %romtype revf. *)

(* Parameters *)
(* %macro CHANNEL_CONTROL         'prm0'. *)
(* %macro MATCH_RATE              'prm1'. *)
%macro TRANSMIT_DATA           'prm2'.
(* %macro DATA_SIZE               'prm3'. *)
(* %macro ACTUAL_BIT_COUNT        'prm4'. *)
%macro TxD_SHFT_REG            'prm5'.

(**********************************************************************)
(*                                                                    *)
(* State 1: Initialisation                                            *)
(*                                                                    *)
(**********************************************************************)

(* prim specified by parameter passed by %include in calling file *)

%entry  ram p <- @CHANNEL_CONTROL; start_address *;disable_match;
name = INIT_TRANSMIT;
cond hsr1 = 1,  hsr0 = 1.

INIT_TRANSMIT:   chan config := p, enable_mtsr.
                 au   diob := max;                (*SET TDRE-BIT*)
                 ram  p <- @MATCH_RATE.
                 chan pin  := high, pac := no_change;
                 au   ert := tcr1 + p;
                 clear  flag0;
                 chan write_mer, neg_tdl, neg_mrl, neg_lsl.
                 ram  diob -> @TRANSMIT_DATA;
                 end.

(**********************************************************************)
(*                                                                    *)
(* State 2: POLLING TDRE                                              *)
(*                                                                    *)
(* Wait for a clear TDRE-Bit and then set the flag0 to indicate a     *)
(* running transmission, send the Start-Bit and set the TDRE-BIT      *)
(**********************************************************************)

%entry ram diob <- @MATCH_RATE; start_address *; disable_match;
name = SEND_START_BIT;
cond hsr1 = 0,  hsr0 = 0,  m/tsr = 1, lsr = x,  pin = x, flag0 = 0.

                 au   ert := ert + diob;
                 ram  p <- @TRANSMIT_DATA.
                 au   nil := p, ccl.
                 if N = 1 then goto DONOTHING.
                 chan write_mer, neg_mrl, neg_lsl, neg_tdl.

SEND_START_BIT:  ram  diob <- @DATA_SIZE.
                 chan pac := high_low;
                      set flag0; cir.       (*now send data and IRQ *)
                 ram  diob -> @ACTUAL_BIT_COUNT.
                 au   p := p + max;          (*set TDRE-Bit = MSB*)
                 ram  p -> @TxD_SHFT_REG.
                 ram  p -> @TRANSMIT_DATA;
                 end.

(**********************************************************************)
(*                                                                    *)
(*          Transmit Bits                                             *)
(*                                                                    *)
(* Read the Data and shift the LSB-Bit out, then write the shifted    *)
(* value into the TxD_SHFT_REG and decrement the number               *)
(* ACTUAL_BIT_COUNT and store it back.                                *)
(**********************************************************************)

%entry  ram diob <- @MATCH_RATE; start_address *; disable_match;
name = SEND_DATA_BITS;
cond hsr1 = 0,  hsr0 = 0,  m/tsr = 1,  lsr = x,  pin = x,  flag0 = 1.

SEND_DATA_BITS:  au  ert := ert + diob;
                 ram p <- @ACTUAL_BIT_COUNT.
                 chan write_mer, neg_tdl, neg_lsl, neg_mrl.
                 au   p := p - 1, ccl.
                 if   N = 1 then goto SEND_STOP_BIT.
                 ram  p -> @ACTUAL_BIT_COUNT.
                 ram  p <- @TxD_SHFT_REG.
                 au   p :=>> p, ccl.                  (* shift right *)
                 if   C = 1 then goto SEND_HIGH_BIT.
                 ram  p -> @TxD_SHFT_REG.
SEND_LOW_BIT:    chan pac := high_low;
                 end.

SEND_HIGH_BIT:   chan pac := low_high;
                 end.

SEND_STOP_BIT:   chan pac := low_high;
                 clear flag0;
                 end.

(**********************************************************************)
(*     UNDEFINED ENTRIES - execute an end.                            *)
(**********************************************************************)
%entry start_address DONOTHING; disable_match;
name = UART_UNDEF;
cond hsr1 = 0, hsr0 = 1.

%entry start_address DONOTHING; disable_match;
name = UART_UNDEF;
cond hsr1 = 1, hsr0 = 0.

%entry start_address DONOTHING; disable_match;
name = UART_UNDEF;
cond hsr1 = 0,  hsr0 = 0,  m/tsr = 0,  lsr = 1,  pin = x,  flag0 = x.

UART_UNDEF:
(* DONOTHING: *)      end.

(* EOF *)
